Representative Patents Drafted by Suneel Arora

• U.S. Patent No. 6,174,291 - Optical Biopsy System and Methods for Tissue Diagnosis.
  Tissue is characterized by fluorescence spectroscopy without requiring fluorescence-enhancing agents.
  
  
• U.S. Patent No. 6,169,918 - Cardiac Rhythm Management System With Cross-Chamber Soft Blanking.
  Detection of a cross-chamber event associated with the second chamber increase a time-varying first chamber sensing threshold, but does not result in completely ignoring signals associated with the first chamber for an appreciable amount of time. As a result, actual first chamber events are less likely to escape detection, such that critically important therapy is properly delivered to the patient.
  
  
• U.S. Patent No. 6,140,181 - Memory Using Insulator Traps.
  Dynamic or nonvolatile binary or multi-state data is stored via a single electron charge on point defect trap sites in an insulator.
  
  
• U.S. Patent No. 6,128,529 - Device Providing Pacing and Antitachyarrhythmia Therapies.
  Atrial-based timing reduces inappropriate anti-tachyarrhythmia therapy. A ventricular-atrial (VA) time interval is increased, when an ventricular activation is sensed during an atrial-ventricular (AV) time interval, by the time remaining after the sense in the immediately preceding AV interval.
  
  
• U.S. Patent No. 6,128,529 - Device Providing Pacing and Antitachyarrhythmia Therapies.
  Atrial-based timing reduces inappropriate anti-tachyarrhythmia therapy. A ventricular-atrial (VA) time interval is increased, when an ventricular activation is sensed during an atrial-ventricular (AV) time interval, by the time remaining after the sense in the immediately preceding AV interval.
  
  
• U.S. Patent No. 6,117,619 - Low Temperature Anti-Reflective Coating for IC Lithography.
  An optically absorptive first layer is deposited by low pressure chemical vapor deposition (LPCVD). An optically transmissive second layer is oxidized at low temperatures on the first layer, providing an optical impedance matching an adjacent photoresist, minimizing reflections, and reducing swing effect and notching.
  
  
• U.S. Patent No. 6,110,233 - Wound Multi-Anode Capacitor with Offset Anodes.
  Anodes in a multi-anode stack are offset to reduce mechanical stresses in the capacitor windings. This increases its reliability, allows a smaller diameter mandrel opening, and increases the energy density per unit volume of the capacitor and allowing its volume to be reduced for use in an implantable medical device.
  
  
• U.S. Patent No. 6,097,223 - Drive Current Modulated Output Driver.
  A high speed output driver tolerates appreciable interconnection capacitance. It reduces the current sourced or sunk during switching as the voltage approaches power supply or ground. This reduces ringing and improves switching time.
  
  
• U.S. Patent No. 6,091,991 - Atrial Antitachyarrhythmia Therapy.
  Atrial anti-tachyarrhythmia therapy is delivered after a programmable delay period following an indication of susceptibility to ventricular tachyarrhythmia (VT). This reduces the risk of reinducing VT.
  
  
• U.S. Patent No. 6,076,015; 6,161,042 - Rate Adaptive Cardiac Rhythm Management Device Using Transthoracic Impedance.
  A device extracts ventilation information from transthoracic impedance obtained by a weighted demodulation of a four-phase AC stimulus. An adaptive lowpass filter, with a cutoff frequency based on heart rate, removes cardiac stroke information.
  
  
• U.S. Patent No. 6,072,209 - 4F2 Folded Bit Line DRAM With Buried Bit and Word Lines.
  A memory cell includes buried bit and word lines with access transistors formed as a vertical structure on the bit lines. A pair of vertically-oriented word lines, which are located in each isolation trench orthogonal to the bit lines, gate alternate access transistors.
  
  
• U.S. Patent No. 6,067,471 - Atrial and Ventricular Implantable Defibrillator and Lead System.
  A defibrillator provides atrial, or both atrial and ventricular, anti-tachyarrhythmia therapy. It includes a supraventricular electrode disposed in the atrium and superior vena cava.
  
  
• U.S. Patent No. 6,031,263 - DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate.
  A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate and an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages.
  
  
• U.S. Patent No. 6,016,446 - Cardiac rhythm management system including nonlinear, non-blanking sense amplifier.
  A system provides a nonlinear gain characteristic that amplifies intrinsic heart activity signals and attenuates detected pacing pulses. The system determines whether a pacing pulse triggered a heart contraction, and adjusts pacing pulse energy accordingly.
  
  
• U.S. Patent No. 6,010,532 - Dual path implantable hearing assistance device.
  A dual path implantable hearing assistance system transduces sound vibrations of the malleus in one or both ears into electrical signals, then processes and transduces the output signals into mechanical vibrations provided to the stapes in one or both ears.
  
  
• U.S. Patent No. 6,005,955 - Middle ear transducer.
  An implantable hearing aid transducer is coupled to a middle ear only through an auditory element in the middle ear, such as the tympanic membrane, malleus, incus, stapes, or in the inner ear, such as the oval window, round window, vestibule, or semicircular canals. It need not be secured to a temporal bone.
  
  
• U.S. Patent No. 5,999,856 - Implantable hearing assistance system with calibration and auditory response testing.
  A hearing assistance system includes electric response audiometry (ERA) functions, such as for diagnostic, self-calibration, frequency-response parameter adjustment, feedback self-testing, and automatic gain control (AGC) purposes.
  
  
• U.S. Patent No. 5,993,376 - Electromagnetic input transducers for middle ear sensing.
  A hearing assistance system senses vibrations at the tympanic membrane, malleus, incus, or other auditory element. A resulting electrical signal on the coil is processed, then provided to an output stimulator for mechanical or electrical stimulation of the cochlea.
  
  
• U.S. Patent No. 5,973,356 - Ultra high density flash memory.
  A flash EEPROM memory cell array provides increased storage capacity. Each memory cell includes a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar.
  
  
• U.S. Patent No. 5,954,628 - Capacitive input transducers for middle ear sensing.
  A hearing assistance system includes a capacitive sensor detecting vibrations at the tympanic membrane, malleus, incus, or other auditory element. A resulting electrical output signal is provided to an output stimulator for assisting hearing.
  
  
• U.S. Patent No. 5,936,274; 6,143,636 - High density flash memory.
  A flash EEPROM includes a memory cell array. Each cell includes a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar.
  
  
• U.S. Patent No. 5,935,166 - Implantable hearing assistance device with remote electronics unit.
  A subcranially implantable hearing system is remotely situated from the ear, such as in the pectoral region, rather than in the mastoid portion of the temporal bone. This increases available volume, and allows a bigger battery.
  
  
• U. S. Patent Nos. 5,930,175; 6,023,427 - Voltage pump switch.
  A voltage pump switch multiplexes: (1) a negative voltage for erasing a floating gate transistor; and (2) extreme positive voltages for programming or reading the floating gate transistor. It includes a charge pump for providing a gate voltage to the multiplexing switches.
  
  
• U.S. Patent No. 5,926,740 - Graded anti-reflective coating for IC lithography.
  An antireflective coating (ARC) is graded from SiOC, at its interface with the photoresist, to SiC or Si, in a direction away from the photoresist. Photolithographic limitations such as swing effect and reflective notching are reduced.
  
  
• U.S. Patent Nos. 5,892,720; 6,002,623 - Semiconductor memory with test circuit.
  A test circuit reduces testing time by concurrently writing a row of memory cells to a logic level, then reading. Any faulty cells discharge both true and complementary data lines through a diode.
  
  
• U.S. Patent No. 5,892,703 - Memory architecture and decoder addressing.
  Interstitial separations between memory cell arrays include longitudinal streets with row decoders and latitudinal streets with column decoders and sense amplifiers. The street intersections include decoder control circuits requiring fewer drivers, which can be staggered or laterally offset.
  
  
• U.S. Patent No. 5,886,368 - Transistor with silicon oxycarbide gate.
  A silicon oxycarbide (SiO) gate FET reduces the gate-insulator barrier energy, improving memory write and erase functions. In a light detector or imager, it provides sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate and is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
  
  
• U.S. Patent Nos. 5,865,749; 6,063,034 - Blood flow meter.
  A strobed blood flow meter provides periodic measurements of blood flow velocity or volumetric blood flow over a cardiac cycle at reduced average power consumption. Continuous wave Doppler, pulsed Doppler, laser Doppler, transit time, electromagnetic flow, and thermal dilution techniques are included.
  
  
• U.S. Patent Nos. 5,852,581; 5,898,629 - Method of stress testing memory integrated circuits.
  Burn-in voltages are delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An “all row high” test cycles word lines between logic levels. A “half row high” test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
  
  
• U.S. Patent No. 5,842,967 - Contactless transducer stimulation and sensing of ossicular chain.
  An implantable hearing aid system for the middle ear utilizes a pair of permanent magnets to repulsively engage a transducer with an auditory elements in a middle ear.
  
  
• U.S. Patent Nos. 5,834,813; 6,040,608 - Field-effect transistor for one-time programmable nonvolatile memory element.
  A one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element without adding complexity to a very large scale integrated (VLSI) circuit process.
  
  
• U.S. Patent No. 5,831,923; 6,108,260 - Antifuse detect circuit.
  An antifuse detect circuit senses the conductance of a programmable element, such as an antifuse or fuse, and provides a logic output corresponding to the state of the programmable element. The circuit allows quick and accurate sensing of the state of the programmable element, even when it is only marginally conductive.
  
  
• U.S. Patent No. 5,815,429 - Antifuse programmer.
  A self-timing antifuse programmer monitors antifuse programming current until it reaches a current trip point. This initiates a delay period determined by charging a capacitor with a scaled copy of the antifuse current until a trip point voltage is reached. More resistive antifuses receive a longer programming time.
  
  
• U.S. Patent No. 5,774,408 - DRAM Architecture With Combined Sense Amplifier Pitch.
  Layout area is reduced by sharing and arranging sense amplifiers. Each memory cell region has one N-sense amplifier for every two digit line pairs, and one P-sense amplifier for each digit line pair. Each N-sense amplifier is shared between two memory array portions.
  
  
• U.S. Patent Nos. 5,768,202; 5,905,686 - Fast Sense Amplifier For Small Voltage Differences.
  A control signal activating a P-sense amplifier is capacitively coupled to two digit lines, further increasing the voltage of the more positive line. The other digit line is more positive than the equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier.
  
  
• U.S. Patent Nos. 5,762,583; 5,899,847 - Piezoelectric film transducer.
  An electromechanical transducer film is carried by a mount secured to the middle ear, constrained by the mount or by the mount and an auditory element. Mechanical vibrations are transduced into electrical signals.
  
  
• Arora et al. U.S. Patent Nos. 5,757,167; 5,847,551 - Voltage Regulator.
  When large currents are drawn from a battery powering the voltage regulator, switches decouple it from the battery and couple it to a stable boost converter output voltage. Controlled switch conductances provide operation over a wide range of output load currents.
  
  
• U.S. Patent Nos. 5,730,699; 5,879,283; 5,997,466 - Implantable Hearing System With Multiple Transducers.
  Mechanical-to-electrical or electrical-to-mechanical frequency response is optimized by multiple transducers of substantially nonidentical frequency responses, such as by using transducers of different dimensions, different number of transducer elements, different material properties, etc.
  
  
• U.S. Patent Nos. 5,723,375; 5,973,344 - EEPROM Transistor for a DRAM.
  A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Existing DRAM process steps implement an EEPROM floating gate transistor nonvolatile memory element.
  
  
• U.S. Patent No. 5,707,338 - Stapes Vibrator.
  A piezoelectric transducer vibrates a stapes from within its inner circumference, such as between its neck and footplate.
  
  
• U.S. Patent No. 5,699,014 - Linear Amplifier.
  An amplifier includes active load FETs biased in a nonsaturation (linear) region by a varying gate terminal voltage that matches the temperature dependence of the load FET output conductance to that of the input FET transconductance. Nonlinearity in the load FET output conductance cancels that of the input FET transconductance.
  
  
• U.S. Patent No. 5,684,809 - Semiconductor Memory with Test Circuit.
  A row of memory cells is concurrently written to a logic level, then read. Faulty memory cells will discharge both data lines through a diode. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row. This reduces testing time.
  
  
• U.S. Patent Nos. 5,679,593; 5,990,538 - High Resistance Integrated Circuit Resistor.
  By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. This obtains a high resistance using standard CMOS process steps.
  
  
• U.S. Patent No. 5,668,751 - Antifuse Programming Method and Apparatus.
  A self-timing antifuse programmer monitors a programming current through the antifuse until it reaches a current trip point and initiates a delay period that is based on the antifuse current. More resistive antifuses receive a longer programming time.